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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16879
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
The PD16879 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOSFET output circuit. Because it uses MOSFETs in its output stage, this driver IC consumes less power than conventional driver ICs that use bipolar transistors. Because the PD16879 controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. As a result, the performance of the application set can be improved and the size of the set has been reduced. This IC employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. The PD16879 is a housed in a 38-pin shrink SOP to contribute to the miniaturization of application set. This IC can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
FEATURES
* Four H bridge circuits employing power MOS FETs * Current-controlled 64-step micro step driving * Motor control by serial data (8 bits x 13 bytes) PWM-frequency, output current and number of output pulse can be setting by serial data. * 3-V power supply. Minimum operating voltage: 2.7 V * Low consumption current. VDD pin current (operating mode) * Power save circuit bult in. VDD pin current (power save mode) : 100 A (MAX.) VDD pin current (power save mode) : 300 A (MAX.) * 38-pin shrink SOP (7.62 mm (300)) fCLK: OFF state fCLK: 4.5 MHz input : 3 mA (MAX.)
ORDERING INFORMATION
Part Number Package 38-pin plastic shrink SOP (7.62 mm (300))
PD16879GS-BGG
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14188EJ1V0DS00 (1st edition) Date Published July 2000 N CP(K) Printed in Japan
(c)
2000
PD16879
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
When mounted on a glass epoxy board (100 mm x 100 mm x 1 mm, 15% copper foil)
Parameter Supply voltage Symbol VDD VM Input voltage Reference voltage H bridge drive current VIN VREF IM(DC) IM(pulse) Power consumption Peak junction temperature Storage temperature PT TCH(MAX) Tstg External input DC PW < 10 ms, Duty < 5 % Conditions Control part Output part Rating -0.5 to +6.0 -0.5 to +11.2 -0.5 to VDD + 0.5 0.5 0.15 0.3 1.0 150 -55 +150 Unit V V V V A/ch A/ch W C C
RECOMMENDED OPERATING RANGE (TA = +25C)
When mounted on a glass epoxy board (100 mm x 100 mm x 1 mm, 15% copper foil)
Parameter Supply voltage Symbol VDD VM Input voltage Reference voltage EXP pin input voltage EXP pin input current H bridge drive current VIN VREF VEXPIN IEXPIN IM(DC) IM(pulse) Clock frequency (OSCIN) Clock frequency amplitude Serial clock frequency Video sync signal width LATCH signal wait time SCLK wait time SDATA setup time SDATA hold time Reset signal pulse width Operating temperautre Peak junction temperature fCLK VfCLK fSCLK PW(VD) t(VD-LATCH) t(SCLK-LATCH) tsetup thold tRST TA TCH(MAX) fCLK = 4.5 MHz Refer to Fig. 1 250 400 400 80 80 100 -10 85 125 DC PW < 10 ms, Duty < 5% COSC = 68 pF, VREF = 250 mV -0.1 -0.2 3.9 0.7 x VDD 4.5 External input Control part Output part Conditions MIN. 2.7 4.0 0 225 250 TYP. MAX. 5.5 11 VDD 275 VDD 100 +0.1 +0.2 6.0 VDD 5.0 Unit V V V mV V
A
A/ch A/ch MHz V MHz ns ns ns ns ns
s
C C
2
Data Sheet S14188EJ1V0DS00
PD16879
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, TA = 25C, VDD = 3 V, VM = 5.4 V, fCLK = 4.5 MHz, COSC = 68 pF, CFIL = 1000 pF, VREF = 250 mV, EVR = 100 mV (10000))
Parameter Off state VM pin current Operating state VDD pin current VDD pin current Power save state VDD pin current Symbol IMO(RESET) IDD IDD(RESET) IDD(PS)1 IDD(PS)2 High level input voltage Low level input voltage Input hysteresis vosltage Monitor output voltage 1 (EXTOUT , ) VIH VIL VH VOM(H) VOM(H) VOM(L) VOM(L) Monitor output voltage 2 (EXP 0,1 open drain) High level input current Low level input current Reset pin high level input current Reset pin low level input current H bridge ON resistance Chopping frequency
Note 1
Conditions No load, Reset period Output open Reset period tCLK = off fCLK = 4.5 MHZ LATCH, SCLK, SDATA, VD, VD RESET, OSCIN, VREFsel
MIN.
TYP.
MAX. 1.0 3.0 100 100 300
Unit
A
mA
A A A
V
0.7 x VDD 0.3 x VDD 0.3
V V V
4th byte
0.9 x VDD -0.3 0.9 x VDD 0.1 x VDD 1.0 -1.0 1.0 -1.0 6.0 Refer to table 1 (TYP.) 225 250 275 250 0.1 x VDD
V
VOEXP(H) VOEXP(L) IIH IIL IIH(RST) IIL(RST) RON fOSC VREF
Pull up (VDD) IOEXP = 100 A VIN = VDD VIN = 0 VRST = VDD VRST = 0 IM = 100 mA, upper + lower
V V
A A A A
kHz mV ns mA
Internal reference voltage VD delay time
Note 2
tVD
IM L = 15 mH/R = 70 ( 1 kHz) RS = 6.8 , fOSC = 72.58 kHz EVR = 220 mV (11100) EVR = 200 mV (11010) VREF = 250 mV external input Minimum step IM = 100 mA 370 53
Sin wave peak output current Note 3 (reference value)
FIL pin voltage
Note 4
VEVR
Note 4
400
430
mV
FIL pin step voltage
VEVRSTEP tONH tOFFH
20 2.0 2.0
mV
H bridge turn on time
Note 5
s s
H bridge turn off time
Note 5
Notes 1. When data are less than 7 (000111), PWM chopping doesn't do it, and output pulse doesn't occur. When data are beyong 49, PWM chopping frequency becomes a 225 kHz fixation. 2. By OSCIN and VD sync circuit 3. FB pin is monitored. 4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin. 5. 10% to 90% of the pulse peak value without filter capacitor (CFIL)
Data Sheet S14188EJ1V0DS00
3
PD16879
Fig 1. Delay Time of Serial Data
VD
VD t(VD-LATCH) LATCH 104 clocks (8 bits x 13 bytes)
SCLK
t(SCLK-LATCH) Ignored because LATCH is at low level
t(SCLK-LATCH) Ignored because LATCH is at low level
LATCH
50%
SDATA 50%
D1
D2 50%
D3
SCLK
t(SCLK-LATCH)
tsetup thold
Table 1. Chopping Frequency (3rd byte D5 to D0 bit data, fCLK = 4.5 MHz) Typical Value
Input data D5 to D0 bit 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 Chopping frequency (kHz) 35.71 40.18 45.00 50.00 53.57 59.21 62.50 68.18 72.58 77.59 80.36 86.54 90.00 93.75 97.83 102.27 107.14 112.50 118.42 118.42 125.00 Input data D5 to D0 bit 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 Chopping frequency (kHz) 132.35 132.35 140.63 140.63 150.00 150.00 160.71 160.71 160.71 173.08 173.08 173.08 187.50 187.50 187.50 204.55 204.55 204.55 204.55 225.00
Note When data are less than 7 (000111), PWM chopping doesn't do it, and output pulse doesn't occur. When data are beyond 49, PWM chopping frequency becomes a 225 kHz fixation.
4
Data Sheet S14188EJ1V0DS00
PD16879
Table 2. Relation Between Rotation Angle, Phase Current, and Vector Quantity (64-DIVISION MICRO STEP) (Value of PD16879 for reference)
STEP Rotation angle () MIN. A phase current TYP. 0 9.8 19.5 29.1 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 MAX. - 17.0 26.5 36.1 45.3 54.1 62.6 68.4 75.7 82.3 88.1 93.2 97.4 100.7 103 - - MIN. - - 93.2 90.7 87.4 83.2 78.1 72.3 65.7 58.4 48.6 40.1 31.3 22.1 12.4 2.5 - B phase current TYP. 100 100 98.1 95.7 92.4 88.2 83.1 77.3 70.7 63.4 55.6 47.1 38.3 29.1 19.5 9.8 0 MAX. - - 103 100.7 97.4 93.2 88.1 82.3 75.7 68.4 62.6 54.1 45.3 36.1 26.5 17.0 - Vector quantity TYP. 100 100.48 100 100.02 100.02 99.99 99.98 99.97 99.98 99.97 99.98 99.99 100.02 100.02 100 100.48 100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90
- 2.5 12.4 22.1 31.3 40.1 48.6 58.4 65.7 72.3 78.1 83.2 87.4 90.7 93.2 - -
Remark These data do not indicate guaranteed values.
Data Sheet S14188EJ1V0DS00
5
PD16879
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LGND COSC FILA FILB FILC FILD VREF VDD VM3 D2 FBD D1 VM4 C2 FBC C1 EXP0 EXP1 VREFsel RESET OSCOUT OSCIN SCLK SDATA LATCH VD VD B2 FBB B1 VM2 A2 FBA A1 VM1 EXT EXT PGND 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
6
Data Sheet S14188EJ1V0DS00
PD16879
PIN FUNCTION
Package: 38-pin plastic shrink SOP
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin name LGND COSC FILA FILB FILC FILD VREF VDD VM3 D2 FBD D1 VM4 C2 FBC C1 EXP0 EXP1 VREFsel PGND EXT EXT VM1 A1 FBA A2 VM2 B1 FBB B2 VD VD LATCH SDATA SCLK OSCIN OSCOUT RESET Control circuit GND pin Chopping capacitor connection pin Pin function
1 ch filter capacitor connection pin 2 ch filter capacitor connection pin 1 ch filter capacitor connection pin 2 ch filter capacitor connection pin
Reference voltage input pin (250 mV typ) Control circuit supply voltage input pin Output circuit supply voltage input pin
Note 1
2 ch output pin 2 ch sense resistor connection pin 2 ch output pin
Output circuit supply voltage input pin
1 ch output pin 1 ch sense resistor connection pin 1 ch ouptut pin
External extension pin (open drain) External extension pin (open drain) Reference voltage select pin Output circuit GND pin
Note 1
ch logic circuit monitor pin ch logic circuit monitor pin
Output circuit supply voltage input pin
1 ch output pin 1 ch sense resistor connection pin 1 ch output pin
Output circuit supply voltage input pin
2 ch output pin 2 ch sense resistor connection pin 2 ch output pin
Video sync signal input pin Video sync signal input pin LATCH signal input pin Serial data input pin Serial clock input pin (4.5 MHz typ) Original oscillation input pin (4.5 MHz typ) Original oscillation output pin Reset signal input pin
Note 2 Note 2
Remark Plural terminal (VM) is not only 1 terminal and connect all terminals. Notes 1. A standard voltage to use is chosen. VREFsel: High level VREFsel: Low level using external input VREF using internal reference voltage (VREF pin fixed GND level)
2. Input the video sync singnal to VD pin or VD pin. A free terminal is to do the following treatment. When input VD: VD pin connect to VDD pin. When input VD: VD pin connect to GND pin.
Data Sheet S14188EJ1V0DS00
7
PD16879
I/O PIN EQUIVALENT CIRCUIT
Pin name VD VD LATCH SDATA SCLK OSCIN RESET VREFsel Equivalent circuit
VDD
Pin name VREF
Equivalent circuit
VDD Internal 250 mV
PAD
PAD VREFsel
OSCOUT EXT EXT
PAD
VDD
EXP0 EXP1
VDD
PAD
FILA FILB FILC FILD
PAD
VDD
Buffer
A1, A2 B1, B2 C1, C2 D1, D2
VM
Parasitic diodes
PAD
FB
8
Data Sheet S14188EJ1V0DS00
BLOCK DIAGRAM
Remark Plural terminal (VM) is not only 1 terminal and connect all terminals.
OSCIN 36 RESET VDD VM1 VM2 VM3 VM4 38 8 23
OSCOUT 37
VD 32
VD 31
SCLK 35
SDATA 34
LATCH 33
EXP0 EXP1 17 18
VREFsel 19
VREF 7
x2 SERIAL-PARARELLE DECODER
Vref select
250 mV B.G.R
27 9 1/N 13 2 CURRENT SET OSC CURRENT SET 21 22 EXT EXT PULSE GENERATER EXTOUT SELECTOR
Data Sheet S14188EJ1V0DS00
COSC
+ + - + + - + - +
+
VM LGND PGND 1 20 H BRIDGE
FILTER
-
+
FILTER
VM
VM
FILTER
VM
FILTER
H BRIDGE
H BRIDGE
H BRIDGE
1ch
2ch
1ch
2ch
25 FBA
24 A1
26 A2
3 FILA
29 FBB
28 B1
30 B2
4 FILB
15 FBC
16 C1
14
5
11 FBD
12 D1
10 D2
6 FILD
C2 FILC
PD16879
9
10
CPU 100 k x 2 4.5 MHz TYP. Using internal reference OSCOUT 37 VD 32 VD 31 SCLK SDATA LATCH 35 34 33 EXP0 EXP1 17 18 VREFsel 19 VREF 7 OSCIN 36 RESET REGULATOR 2.7 V to 5.5 V VDD VM1 VM2
Data Sheet S14188EJ1V0DS00
EXAMPLE OF STANDARD CONNECTION
38 8 23 27 9 13 2
CURRENT SET CURRENT SET
x2 SERIAL-PARALLELE DECODER PULSE GENERATOR
Vref select
250 mV B.G.R
VM3 VM4 COSC BATTERY 4.0 V to 11 V 68 pF
1/N
EXTOUT SELECTOR 21 22
+
EXT EXT
OSC
+ + -+ + FILTER -+ FILTER -+
VM LGND PGND 1 20 H BRIDGE 1ch 25 FBA 6.8 x 2 24 A1
FILTER
-+
VM
VM
VM
FILTER
H BRIDGE 1ch 29 28 B1 30 4 B2 FILB 15 FBC 6.8
H BRIDGE 1ch 16 C1 14 5 11
H BRIDGE 1ch 12 D1 10 6 D2 FILD 1000 pF
26 3
A2 FILA FBB
C2 FILC FBD 6.8 1000 pF
1000 pF x 2 MOTOR 1 MOTOR 2
PD16879
TIMING CHART (1)
Initialization RESET VD VD S1 LATCH DATA SCLK OSCOUT
Start point wait (FF1) Start point wait+ Start point magnetize wait (FF2)
S2
S3
S4 pulse 0
S5 PS
S6 PS
S7 release PS S8
S9 Enable
S10 release PS S11
S12 data error S13 normal data
S14
S7 S1 S2 S2 S3 S3 S4 S4 S4
H level fixation It reverts from the VD start after a PS release. L level fixation
S8 S8 S9
S9 S10
S10 S11
S11 S12
S12 S13
S13 S14
Data Sheet S14188EJ1V0DS00
ENABLE OUTNote 1 CHOPPING EXP 0, 1
S2 S3 Stop from LATCH
L level fixation Start from LATCH
EXP can be change in PS period too.
Pulse count is done in enable period too
PULSE OUT PULSE GATE (FF3) PULSE CHECKNote 2 (FF7) CHECK SUMNote 3
Pulse is nothing because pulse data is "0"
S4
S5 to S7
Pulse is nothing because PS data
S8
S9
S10
S11
S13
Pulse is nothing because error data.
Output L level because error data
SCLK SDATA 1st byte 13th byte
D0
D1
D2
D3
D4
D5
D6
D7
(LSB) Data is held at rising edge SCLK
Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low to high, and at the falling edge of FF2 when the level changes from high to low. 2. FF7 is an output signal that is used to check for the presence or absence of a pulse in the serial data, is updated at the falling edge of LATCH and reset once at the rising edge of LATCH. If CHECK SUM is other than "00h", FF7 goes low, inhibiting pulse output, even if a pulse is generated. 3. CHECK SUM output is updated at the falling edge of LATCH.
PD16879
11
PD16879
TIMING CHART (2)
CLK (PULSE OUT)
MOB
(CW mode) Current direction: A2 to A1 H bridge , 1ch output Current direction: A1 to A2
Current direction: B2 to B1 H bridge , 2ch output Current direction: B1 to B2
Current direction: B2 to B1
(Expanded view) CW mode CCW mode CW mode
CLK PULSE OUT Position No. 1 2 3 4 5 6 5 4 3 2 3 4
Note CW mode : Position No is incremented. CCW mode: Position No is decremented.
CCW H bridge 1ch output CW CCW CW
CW CW
H bridge 2ch output
CCW CW CW
CCW
Remarks 1. The current value of the actual wave is approximated to the value shown on the page 5. 2. The C1, C2, D1, and D2 pins of channel correspond to the A1, A2, B1, and B2 pins of channel. 3. The CW mode is set if the D6 bit of the fifth and ninth bytes of the data is "0". 4. The CCW mode is set if the D6 bit of the fifth and ninth bytes of the data is "1".
12
Data Sheet S14188EJ1V0DS00
PD16879
STANDARD CHARACTERISTICS CURVES
PT vs. TA characteristics 1.2 7.0 6.0
VDD pin current IDD (mA)
IDD vs. VDD characteristics TA = 25C operating
Total power dissipation PT (W)
1.0
0.8 125C/W 0.6
5.0 4.0 3.0 2.0 1.0 0
0.4
0.2
0 -20
0
100 20 40 80 60 Ambient temperature TA (C)
120
6 1 2 3 5 4 Control circuit supply voltage VDD (V)
IDD(RESET) vs. VDD characteristics 350
VDD pin current (PS) IDD(PS1), IDD(PS2) ( A) VDD pin current (RESET) IDD(RESET) ( A)
IDD(PS) vs. VDD characteristics TA = 25C PS mode
TA = 25C RESET 300 250 200 150 100 50 0 6 1 2 3 5 4 Control circuit supply voltage VDD (V)
600 500 IDD(PS)2 400 300 200 IDD(PS)1 100 0
6 1 2 3 5 4 Control circuit supply voltage VDD (V)
VIH, VIL vs. VDD characteristics 254 TA = 25C 4.0
Reference voltage VREF (mA) Input voltage VIH, VIL (V)
VREF vs. TA characteristics VDD = 3.0 V VFIL/2
253 252 251 250 249 248 247 246
3.0 VIL 2.0 VIH
1.0
0 6 1 2 3 5 4 Control circuit supply voltage VDD (V)
245 -20
0
100 20 40 80 60 Ambient temperature TA (C)
120
Data Sheet S14188EJ1V0DS00
13
PD16879
IM vs. EVR characteristics 70 Sine wave peak output current IM (mA) 60 50 40 30 20 10 0 50 100 150 250 200 EVR setting voltage EVR (mV) Sine wave peak output current IM (mA) TA = 25C, 70 , 15 mV, VM = 5.4 V RS = 6.8 , fOSC = 72.58 kHz 50
IM vs. VM characteristics TA = 25C, 70 , 15 mH, RS = 6.8 fOSC = 72.58 kHz, EVR = 100 mV (10000) 40
30
20
10
0 2 4 6 12 10 8 Output circuit supply voltage VM (V) RON vs. VM characteristics 8.0 TA = 25C, 70 , 15 mH, VM = 5.4 V fOSC = 72.58 kHz, EVR = 100 mV (10000) TA = 25C H bridge ON resistance RON ()
IM vs. RS characteristics 60 Sine wave peak output current IM (mA)
50
6.0
40
30
4.0
20
2.0
10
0 2 4 6 8 10 12 Current sense resistor RS () 14
0 4 6 8 10 2 12 Output circuit supply voltage VM (V)
RON vs. TA characteristics 8.0 VM = 4.0 V 6.0
H bridge ON resistance RON ()
VM = 5.4 V 4.0 VM = 8.0 V VM = 11 V 2.0
0 -20
0
40 60 80 20 100 Ambient temperature TA (C)
120
14
Data Sheet S14188EJ1V0DS00
PD16879
I/F CIRCUIT DATA CONFIGURATION (fCLK = 4.5 MHz EXTERNAL CLOCK INPUT)
Input data consists of serial data (8 bits x 13 bytes). Input serial data with the LSB first, from the first byte to 13th byte. [1st byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 8 bit data Note input Function First point wait Setting First point wait 227.6 s to 58.03 ms Setting (1 to 255) t = 227.6 s
[2nd byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 8 bit data Note input Function First point magnetize wait Setting First point magnetize wait 227.6 s to 58.03 ms Setting (1 to 255) t = 227.6 s
Note Input other than "0" [3rd byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 1 or 0 6 bit data input Function EXP1 EXP0 Chopping frequency Setting Z/L Z/L
Note 1
Note Input other than "0" [4th byte]
Bit D7 Bit D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 Data Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Function Power save EXT Output Enable
Note 2
Setting OFF/ON
Note 1
Note 1
EXT Output Enable
Note 2
Chopping frequency 35.71 kHz to 225 kHz Setting Note 2 (8 to 48)
Rotation
Note 3
Rotation
Note 3
Pulse out FF7 FF3 Checksum Chopping
Note 4
Pulse out FF7 FF3 FF2 FF1
Notes 1. 2.
Z: High impedance/L: low level 0 to 7 input: PWM and pulse out nothing 49 to 63 input: 225 kHz fixed Refer to 4 page
Notes 1. 2. 3. 4. 5.
Data "1": Normal/Data "0": Power save High: Conducts/Low: Stops High: Reverse (CCW)/Low: Forward (CW) High: Normal data/Low: Error data Select one of D0 to D6 and input "1". If two or more of D0 to D6 are selected, they are positively ORed for output.
Data Sheet S14188EJ1V0DS00
15
PD16879
[5th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 1 or 0 0 5 bit data input Function Enable Rotation Not use Setting
[6th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 8 bit data input Function Setting
ch ON/OFF ch CCW/CW
Not use
channel Pulse Number
channel Current set
channel Note Current set
EVR: 50 to 250 mV Setting (11 to 31)
channel Number of pulse in 1 VD 0 to 1020 pulses Setting (0 to 255) n = 4 Note pulses
Note Fixed to 50 mV if 0 to 10 input. Refer to 4 page.
Note Output pulse is nothing if data input 256, 512, and 768.
[7th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 16 bti data low-order 8 bit data input Function Setting
[8th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 16 bit data High-order 8 bit data input Function Setting
channel Pulse Cycle
channel Pulse cycle 222 ns to 14.563 ms Setting (1 to 65535) t = 222 ns
channel Pulse Cycle
channel Pulse cycle 222 ns to 14.563 ms Setting (1 to 65535) t = 222 ns
Note D0 bit of 7th byte is LSB, and D7 bit of 8th byte is MSB.
[9th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 1 or 0 0 5 bit data input Function Enable Rotation Not use Setting
[10th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 8 bit data input Function Setting
ch ON/OFF ch CCW/CW
Not use
channel Pulse Number
channel Current set
channel Note Current set
EVR: 50 to 250 mV Setting (11 to 31)
channel Number of pulse in 1 VD 0 to 1020 pulses Setting (0 to 255) n = 4 Note pulses
Note Fixed to 50 mV if 0 to 10 input. Refer to 4 page.
Note Output pulse is nothing if data input 256, 512, and 768.
16
Data Sheet S14188EJ1V0DS00
PD16879
[11th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 16 bit data low-order 8 bit data input Function Setting
[12th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 16 bit data high-order 8 bit data input Function Setting
channel Pulse Cycle
channel Pulse cycle 222 ns to 14.563 ms Setting (1 to 65535) t = 222 ns
channel Pulse Cycle
channel Pulse cycle 222 ns to 14.563 ms Setting (1 to 65535) t = 222 ns
Note D0 bit of 11th byte is LSB, and D7 bit of 12th byte is MSB.
[13th byte]
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 8 bit data input Function Checksum Setting Checksum
Note
Note Data is input so that the sum of the first through the 13th bytes is 00h.
Data Sheet S14188EJ1V0DS00
17
PD16879
DATA CONFIGURATION
Input data is composed of the serial data on 8 bits x 13 bytes. Input serial data with the LSB first, i.e., starting from the D0 bit (LSB) of the first byte. Therefore, the D7 bit of the 13th byte is the most significant bit (MSB). The establishment of the delay time to the output from the power supply injection, chopping frequency, output current, number of pulse, pulse cycle, and so on are possible with this product. The PD16879 has an EXT pin for monitoring the internal operations, the parameter to be monitored can be selected by serial data. The PD16879 built in power save function. If set power save mode, consumption current decreased to about 1/10. Input serial data during first point wait time (FF1: high level). This product uses separated external reference clock (fCLK). If they don't input fCLK, this product can't operate normally. The establishment value which shows it in this document is at the time of fCLK = 4.5 MHz. Please be careful because establishment value is different in the case of one except for fCLK = 4.5 MHz.
Detail of Data Configuration
Ho to input serial data is below. [1st byte] The 1st byte specifies the delay between data being read and data being output. This delay is called the first point wait time, and the motor can be driven from that point at which the first point wait time is "0". This time is counted at the rising edge of VD (or falling edge of VD). The first point wait time can be set to 58.03 ms (when a 4.5 MHz clock input) and can be fine-tuned by means of 8-bit division (227.6 s step: with 4.5 MHz clock). Always input data other than "0" to this byte because the first point wait time is necessary for latching data. If "0" is input to this byte, data cannot be updated. Transfer serial data during the first point wait time. Table 3. 1st Byte Data Configuration
Bit Data D7 0 or 1 MSB D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB Data 00000000 00001001 11111111 n First point wait Prohibition About 2.05 ms About 58.03 ms N x 1024/4.5 MHz
18
Data Sheet S14188EJ1V0DS00
PD16879
[2nd byte] The 2nd byte specifies the delay between the first point wait time being cleared and the output pulse being generated. This time called the first point magnetize wait time, and the output pulse is generated from the point at which the start up wait time. The first point magnetize wait time is counted at the falling edge of the first point wait time. The first point magnetize wait time can be set to 58.03 ms (when a 4.5 MHz clock input) and can be fine-tuned by means of 8-bit division (227.6 s step: with 4.5 MHz clock). Always input data other than "0" to this byte because the first point magnetize wait time is necessary for latching data. If "0" is input to this byte, data cannot be updated. Table 4. 2nd Byte Data Configuration
Bit Data D7 0 or 1 MSB D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB Data 00000000 00101001 11111111 n First point wait Prohibition About 9.33 ms About 58.03 ms N x 1024/4.5 MHz
[3rd byte] The 3rd byte sets the chopping frequency and external extension pins (EXP0, EXP1). The chopping frequency sets by bits D0 to D5. The EXP pins goes low (current sink) when the input data is "0", and high (high-impedance state) when the input data is "1". Pull this pin up to VDD for use. Table 5. 3rd Byte Data Configuration
Bit Data EXP1 sets EXP0 sets D7: EXP1 sets D6: EXP0 sets "1": High impedance "1": High impedance D7 0 or 1 D6 0 or 1 D5 0 or 1 MSB Chopping frequency sets "0": Low level (Current sink) "0": Low level (Current sink) D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB
The chopping frequency is set to 0 kHz and to a value in the range of 35.71 kHz to 225 kHz (4.5 MHz clock input). Refer to table 1 (4 page). [4th byte] The 4th byte selects a parameter to be output EXT and EXT pins (logic operation monitor pin). And, power save mode sets too. Table 6. 4th Byte Data Configuration
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
Power save sets
Test parameter select
Data Sheet S14188EJ1V0DS00
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PD16879
The test parameter is selected by bits D0 to D6. There are two EXT pins. EXT indicates the operating status of
channel, and EXT indicates that of channel. The relationship between each bit and each EXT pin is as shown
in Table 7. Table 7. Output Data of Test Parameter
Bit D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Enable Rotation Pulseout FF7 FF3 Checksum Chopping EXT Enable Rotation Pulseout FF7 FF3 FF2 FF1 EXT
If two or more signals that output signals to EXT and EXT are selected, they are positively ORed for output. The meanings of the symbols listed in Table 7 are as follows: Enable Rotation Pulse out FF7 FF3 FF2 FF1 : Output setting (High level: Conducts/Low level: Stops) : Rotation setting (High level: Reverse (CCW)/Low level: Forward (CW)) : Output pulse signal : Presence/absence of pulse in LATCH cycle (Outputs H level if output pulse information exists in serial data.) : Pulse gate (output while pulse exists) : Outputs high level during first point wait time + first point magnetize wait time : Outputs high level during first point wait time transmitted) Chopping : Chopping wave output
Checksum : Checksum output (High level: when normal data is transmitted/Low level: when abnormal data is
Power save mode sets by D7 bit. D7 bit data is "1": Normal mode D7 bit data in "0": Power save mode When power save mode is selected, circuit consumption current can be reduced. Detail of power save function is refer to "About Power Save Mode (25 page)". [5th byte] The 5th byte sets the enable, rotation, and output current of channel. The enable sets by bit D7, the rotation sets by bit D6, and the output current sets by bits D0 to D4. Bit D5 is fixed "0". Bit D5 isn't use. Table 8. 5th Byte Data Configuration ( channel data)
Bit Data Enable sets Rotation sets D7 0 or 1 D6 0 or 1 D5 0 D4 0 or 1 MSB Output current sets D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB
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Data Sheet S14188EJ1V0DS00
PD16879
Enable sets by D7 bit. D7 bit data is "0": Output high impedance (but, internal counter increase) D7 bit data is "1": Output conducts Rotation sets by D6 bit. D6 bit data is "0": Forward turn (CW mode) D6 bit data is "1": Reverse turn (CCW mode) Output current sets by D0 to D4 bits. The 250 mV (typical) voltage input from external source or internal reference voltage is internally doubled and input to a 5-bit D/A converter. By dividing this voltage by 5-bit data, a current setting reference voltage can be set inside the IC within the range of 100 to 500 mV, in units of 20 mV. If external source is used, the VREFsel pin connects VDD pin. If internal reference voltage is used, the VREFsel pin and VREF pin connect GND pin. The 64 steps micro-step (setting reference voltage is maximum) control is possible. Table 9. Output Current Setting Reference Voltage Data ( channel data)
EVR setting 50 mV 60 mV 70 mV 80 mV 90 mV 100 mV 110 mV 120 mV 130 mV 140 mV 150 mV D4 0 0 0 0 0 1 1 1 1 1 1 D3 1 1 1 1 1 0 0 0 0 0 0 D2 0 1 1 1 1 0 0 0 0 1 1 D1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 FIL pin voltage 100 mV 120 mV 140 mV 160 mV 180 mV 200 mV 220 mV 240 mV 260 mV 280 mV 300 mV EVR setting 160 mV 170 mV 180 mV 190 mV 200 mV 210 mV 220 mV 230 mV 240 mV 250 mV D4 1 1 1 1 1 1 1 1 1 1 D3 0 0 1 1 1 1 1 1 1 1 D2 1 1 0 0 0 0 1 1 1 1 D1 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 FIL pin voltage 320 mV 340 mV 360 mV 380 mV 400 mV 420 mV 440 mV 460 mV 480 mV 500 mV
Remark If D0 to D4 bits input "00000" to "01010", EVR value fixed 50 mV (FIL pin voltage fixed 100 mV). FIL pin (peak voltage) is output about double of EVR setting value. [6th byte] The 6th byte sets pulse number during 1VD period of channel. The pulse number setting 1020 pulses maximum. It is set by eight bits in terms of software. However, the actual circuit uses 10-bit counter with the low-order two bits fixed to "0". Therefore, the number of pulses that is actually generated during fall edge of the first point wait time + first point magnetize wait time (FF2) cycle is the number of pulses input x 4. The number of pulses can be set in a range of 0 to 1020 and in units of four pulses. Table 10. 6th Byte Data Configuration ( channel data)
Bit Data D7 0 or 1 MSB D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB Data 00000000 00000001 11111111 n Pulse number/VD 0 4 1020 nx4
Data Sheet S14188EJ1V0DS00
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PD16879
[7th, 8th byte] The 7th byte and 8th byte set the pulse cycle of the channel. The pulse cycle is specified using 16 bits: bits D0 (least significant bit) to D7 of the 7th byte, and bits D0 to D7 (most significant bit) of the 8th byte. The pulse cycle can be set to a value in the range of 222 ns to 14.563 ms in units of 222 ns (with a 4.5 MHz clock). Table 11 (A). 7th Byte Data Configuration ( channel data)
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB
Table 11 (B). 8th Byte Data Configuration ( channel data)
Bit Data MSB D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
[9th byte] The 9th byte sets the enable, rotation, and output current of channel. The enable sets by bit D7, the rotation sets by bit D6, and the output current sets by bits D0 to D4. Bit D5 is fixed "0". Bit D5 isn't use. Table 12. 9th Byte Data Configuration ( channel data)
Bit Data Enable sets Rotation sets D7 0 or 1 D6 0 or 1 D5 0 D4 0 or 1 MSB Output current sets D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB
Enable sets by D7 bit. D7 bit data is "0": Output high impedance (but, internal counter increase) D7 bit data is "1": Output conducts Rotation sets by D6 bit. D6 bit data is "0": Forward turn (CW mode) D6 bit data is "1": Reverse turn (CCw mode) Output current sets by D0 to D4 bits. The 250 mV (typical) voltage input from external source or internal reference voltage is internally doubled and input to a 5-bit D/A converter. By dividing this voltage by 5-bit data, a current setting reference voltage can be set inside the IC within the range of 100 to 500 mV, in units of 20 mV. If external source is used, the VREFsel pin connects VDD pin. If internal reference voltage is used, the VREFsel pin and VREF pin connect GND pin. The 64 steps micro-step (setting reference voltage is maximum) control is possible.
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Data Sheet S14188EJ1V0DS00
PD16879
Table 13. Output Current Setting Reference Voltage Data ( channel data)
EVR setting 50 mV 60 mV 70 mV 80 mV 90 mV 100 mV 110 mV 120 mV 130 mV 140 mV 150 mV D4 0 0 0 0 0 1 1 1 1 1 1 D3 1 1 1 1 1 0 0 0 0 0 0 D2 0 1 1 1 1 0 0 0 0 1 1 D1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 FIL pin voltage 100 mV 120 mV 140 mV 160 mV 180 mV 200 mV 220 mV 240 mV 260 mV 280 mV 300 mV EVR setting 160 mV 170 mV 180 mV 190 mV 200 mV 210 mV 220 mV 230 mV 240 mV 250 mV D4 1 1 1 1 1 1 1 1 1 1 D3 0 0 1 1 1 1 1 1 1 1 D2 1 1 0 0 0 0 1 1 1 1 D1 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 FIL pin voltage 320 mV 340 mV 360 mV 380 mV 400 mV 420 mV 440 mV 460 mV 480 mV 500 mV
Remark If D0 to D4 bits input "00000" to "01010", EVR value fixed 50 mV (FIL pin voltage fixed 100 mV). FIL pin (peak voltage) is output about double of EVR setting value. [10th byte] The 10th byte sets pulse number during 1VD period of channel. The pulse number setting 1020 pulses maximum. It is set by eight bits in terms of software. However, the actual circuit uses 10-bit counter with the loworder two bits fixed to "0". Therefore, the number of pulses that is actually generated during fall edge of the first point wait time + first point magnetize wait time (FF2) cycle is the number of pulses input x 4. The number of pulses can be set in a range of 0 to 1020 and in units of four pulses. Table 14. 10th Byte Data Configuration ( channel data)
Bit Data D7 0 or 1 MSB D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB Data 00000000 00101001 11111111 n Pulse number/VD 0 164 1020 nx4
Data Sheet S14188EJ1V0DS00
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PD16879
[11th, 12th byte] The 11th byte and 12th byte set the pulse cycle of the channel. The pulse cycle is specified using 16 bits: bits D0 (least significant bit) to D7 of the 7th byte, and bits D0 to D7 (most significant bit) of the 8th byte. The pulse cycle can be set to a value in the range of 222 ns to 14.563 ms in units of 222 ns (with a 4.5 MHz clock). Table 15 (A). 11th Byte Data Configuration ( channel data)
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1 LSB
Table 15 (B). 12th Byte Data Configuration ( channel data)
Bit Data MSB D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
[13th byte] The 13th byte is checksum data. Please input the data that sum of the 1st byte to 13th byte is "0". When the sum is "0", the stepping operation continued. If the sum is not "0" because data transmission is abnormal, the stepping operation is inhibited and EXT pin (at the Checksum selecting) is held at low level.
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Data Sheet S14188EJ1V0DS00
PD16879
About Power Save Mode
It is possible that circuit electric current is made small in the power saving (the following PS) mode. Data maintenance just before the PS mode and the maintenance of the phase position are done in the PS mode. Circuit consumption current in the PS mode becomes 300 A (MAX.) at the time of the outside clock (OSCIN) = 4.5 MHz, and becomes 100 A (MAX.) at the time of the outside clock (OSCIN) stopped. It can be reduced in less than 1/10 in normal mode. (How to be within PS mode) The establishment of the PS mode is done by a D7 bits of the 4th byte. Please follow the following process when it is within PS mode. (1) Normal operation (Pulse number > 1, enable: conducts) (2-1) Normal operation (Pulse number = 0, enable: conducts) (2-2) Normal operation (Pulse number = 0, enable: stops) (3) Please input PS data.
(Effective timing of PS mode) * Chopping movement stops at the LATCH falling timing which PS data are contained to. * First point wait count and first point magnetize wait count stop at the next VD rising timing which PS data are contained to. FF1 is fixed on the high level, and FF2 is fixed on low level. * Enable becomes low level at the LATCH falling timing which PS data are contained to. * And, the outside expansion circuit (EXP terminal) works at the time of PS mode too. (PS mode release movement) * Chopping movement resumes at the LATCH falling timing which PS release data are contained to. * First point wait count and first point magnetize wait count resume at the next VD rising timing which PS release data are contained to. * Enalbe becomes high level at the first FF1 falling timing which PS release data are contained to. (When enable data is high level)
Data Sheet S14188EJ1V0DS00
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PD16879
Data Update Timing
The serial data of this product is set and update at the following timing. Table 16. Update Timing of The Data (1)
Data First point wait time Data set LATCH falling edge Update timing Next VD rising edge or, next VD falling edge FF1 falling edge LATCH falling edge LATCH falling edge Refer to 25 page
First point magnetize wait time EXP Chopping Power save
LATCH falling edge LATCH falling edge LATCH falling edge LATCH falling edge
The timing at which data is to be update differ, as shown in Table 17, depending on the enable status. Table 17. Update Timing of The Data (2)
Change of enable Pulse cycle Pulse number Rotation Enable EVR FF2 FF2 FF2 FF2 11 FF2 FF2 FF2 FF1 01 FF2 FF2 FF2 FF2 10 00 - - - - -
LATCH
LATCH
LATCH
VD
LATCH
FF1
FF2
Pulse out
Pulse cycle, Pulse number, Rotation are update Enable is update (at the change of enable: 0 to 1) Output current (EVR) is updated
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Data Sheet S14188EJ1V0DS00
PD16879
Initialization
The IC operation can be initialized as follows: (1) Turns ON VDD. (2) Make RESET input low level signal. In initial mode, the operating status of the IC is as shown in Table 18. Table 18. Operations in Initial Mode
Item Current consumption OSC VD, VD FF1 to FF7 Pulse out EXP0, EXP1 100 A Input of external clock is inhibited. Input inhibited. Low level Low level Low level in the case of (1) above. Previous value is retained in the case of (2) above. Can be accessed after initialization in the case of (1) above. Can be accessed after RESET has gone high level in the case of (2) above. Specification
Serial operation
Step pulse output is inhibited and FF7 is made low level if the following conditions are satisfied. (1) If the set number of pulses (6th/10th byte) is "0". (2) If the checksum value is other than "0". (3) If the first point wait time (FF1) is set to 1VD or longer. (4) If the first point wait time + first point magnetize wait time (FF2) is set to 1VD or longer. (5) If the first point wait time (FF1) is completed earlier than falling timing of LATCH. (6) If VD is not input.
Data Sheet S14188EJ1V0DS00
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PD16879
Hints on correct use
(1) With this product, input the data for first point wait time and first point magnetize wait time. Because the serial data are set or updated by these wait times, if the first point wait time and first point magnetize wait time are not input, the data are not updated. (2) The first point wait time must be longer than LATCH. (3) If the falling of the FF2 is the same as the falling of the last output pulse, a count error occurs, and the IC may malfunction. (4) Transmit the serial data during the first point wait time (FF1). If it is input at any other time, the data may not be transmitted correctly. (5) If the LGND potential is undefined, the data may not be input correctly. Keep the LGND potential to the minimum level. It is recommended that LGND and PGND be divided for connection (single ground) to prevent the leakage of noise from the output circuit.
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Data Sheet S14188EJ1V0DS00
PD16879
PACKAGE DRAWINGS
38-PIN PLASTIC SSOP (7.62 mm (300))
38 20 detail of lead end F G
1 A
19 E
P
L
H I S J
C D M
M
N
S
B K
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 12.70.3 0.65 MAX. 0.65 (T.P.) 0.37 +0.05 -0.1 0.1250.075 1.6750.125 1.55 7.70.2 5.60.2 1.050.2 0.2 +0.1 -0.05 0.60.2 0.10 0.10 +7 3 -3 P38GS-65-BGG-1
Data Sheet S14188EJ1V0DS00
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PD16879
RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions. For soldering methods and conditions other than those recommended, consult NEC. For details of the recommended soldering conditions, refer to information document "Semiconductor Device Mounting Technology Manual".
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 secs max. (210C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt%, ax.) is recommended Package peak temperature: 215C, Time: 40 secs max. (200C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt%, ax.) is recommended. Package peak temperature: 260C; Time: 10 secs max.; Preheating temperature: 120C max; Number of times: once; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt%, ax.) is recommended. Recommended Condition IR35-00-3
VPS
VP15-00-3
Wave soldering
WS60-00-1
Caution Do not use two or more soldering methods in combination.
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Data Sheet S14188EJ1V0DS00
PD16879
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14188EJ1V0DS00
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PD16879
* The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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